1. Field
Embodiments of the present invention generally relate to a method for forming a round bottom silicon trench recess, more specifically, to a method for forming a round bottom silicon trench recess in semiconductor fabrication applications.
2. Description of the Related Art
Reliably producing submicron and smaller features is one of the key technologies for the next generation of very large scale integration (VLSI) and ultra large scale integration (ULSI) of semiconductor devices. However, as the miniaturization of circuit technology is pressed, the shrinking dimensions of interconnects in VLSI and ULSI technology have placed additional demands on the processing capabilities. The multilevel interconnects that lie at the heart of this technology require precise processing of high aspect ratio features, such as vias and other interconnects. Reliable formation of these interconnects is very important to VLSI and ULSI success and to the continued effort to increase circuit density and quality of individual substrates.
As circuit densities increase for next generation devices, the integration densities have been increased by decreasing transistor feature sizes, including gate length and channel length. Decreased channel length may result in short channel effects, which may increase an off-current threshold of the transistors ad can deteriorate refresh characteristics of memory devices having such transistors. In order to eliminate such problems, forming a recess channel for semiconductor device manufacture has been introduced to extend the channel length of the transistors. The recess channel increases a channel length and reduces an ion-implantation concentration, thereby improving a refresh property of the semiconductor device.
In some instances, recess channels may also be configured to have different shapes or features formed within a trench, instead of conventional vertical only trench shapes, so as to further increase surface area or length of the channels to further improve refresh properties. However, formation of such shapes or features often require complicated and multiple process steps to complete the manufacture process, resulting in increases of manufacturing cycle time and cost with decreased process throughput. Furthermore, poor etching selectivity and control occurring during manufacturing processes for such shapes or features in the recess channels may undesirably result in an inaccurate profile control, thereby eventually leading to device failure.
Thus, there is a need for a channel recess etch process for etching a recess area in a semiconductor substrate with low cost and precise process control.